Circuit Schematic learn

This circuit measures the water temperature. this circuit use IC CA3161 and CA3162 for control all, The Temperature Value can’t be keep always while no power supply as It hasn’t EEPROM to save. This circiut will be display for you monitoring only that is make sense to implement in water.

The IC CA3161 is a counter and 7segment LED driver to display amount of temperature on 7segments. About a temperature sensor is a diode which number 1N4148. This is like of the Car Radiator. Connect to the 5 Vdc power supply from Car Battery that you can use a LM7805 for +5Vdc regulation with low cost voltage regulator.

Skema rangkaian pengukur suhu air

The LM340A monolithic 3-terminal positive voltage regulators employ internal current-limiting, thermal shutdown and safe-area compensation, making them essentially indestructible. If adequate heat sinking is provided, they can deliver over 1.0A output current.

The CA3161E is a monolithic integrated circuit that performs the BCD to seven segment decoding function and features constant current segment drivers. When used with the CA3162E A/D Converter the CA3161E provides a complete digital readout system with a minimum number of external parts.

The CA3162E are I2L monolithic A/D converters that provide a 3 digit multiplexed BCD output. They are used with the CA3161E BCD-to-Seven-Segment Decoder/Driver and a minimum of external parts to implement a complete 3-digit display. The CA3162AE is identical to the CA3162E except for an extended operating temperature range.

This is a digital H-V or high voltage AC switcher schema diagram, Switching a high voltage AC requires use of opto couplers to isolate the High Voltage from the micro controller. A basic schema to trigger an SCR is shown in Fig. 67 -lA. This schema has the disadvantage that the blocking voltage of the photon-coupler output device determines the schema-blocking voltage, irrespective of higher main SCR capability. Adding capacitor Cl to the schema, as shown in Fig. 67-lB, will reduce the dV!dt seen by the photoncoupler output device.

 Digital H-V AC Switcher Circuit Diagram

The energy stored in Cl, when discharged into the gate of SCRl, will improve the dildt capability of the main SCR. Using a separate power supply for the coupler adds flexibility to the trigger schema; it removes the limitation of the blocking voltage capability of the photon-coupler output device. The flexibility adds cost and more than one power supply might be necessary for multiple SCRs if no common reference points are available. 67-lC, Rl can be connected to Point A. which will remove the voltage from the coupler after SCRl is triggered. `or to Point B so that the coupler output will always be biased by input voltage.

The former is preferred since it decreases the power dissipation in Rl. A more practical form of SCR triggering is shown in Fig. 67 -IF. Trigger energy is obtained from the anode su]Jply and stored in Cl. Coupler voltage is limited by the zener voltage. This approach permits switching of higher voltages than the blocking voltage capability of the output device of the photon coupler. To reduce the power losses in Rl and to obtain shorter time constants for charging Cl, the zener diode is used instead of a resistor. A guide for selecting the component values would consist of the following steps: Choose Cl in a range of 0.05 to 1 p.F.

The maximum value might be limited by the recharging time constant (RL + R1) C1 while the minimum value will be set by the minimum pulse width required to ensure SCR latching. R2 is determined from peak gate current limits, if applicable, and minimum pulse width requirements. Select a zener diode. A 25-V zener is a practical value, since this will meet the usual gate requirement of 20 V and 20 0. This diode will also eliminate spurious triggering because of voltage transients. Photon coupler triggering is ideal for the SCR`s driving inductive loads. By ensuring that the LASCR latches on, it can supply gate current to SCRl until it stays on.

Alarm clocks are made to wake you up. However, it is quite bothersome to hear the alarm continuously until you get up and put it off. Also, you might fall asleep again. The snooze facility solves this problem to some extent by allowing you to turn the alarm off for a specific period of time by pressing a switch. But here again, you need to look for the snooze switch!

Here is a low-cost solution to these problems. This schema wakes you up gently. It puts off the alarm after a predetermined time and makes it sound again after some time. And this process is automatic. You don’t need to press any switch, thanks to timer IC NE555, CMOS NAND gate CD4011, and a few discrete components.

There are two types of auto-snooze diagram: one for a digital alarm clock with snooze facility (Fig. 1) and the other for a digital alarm clock without snooze facility (Fig. 2).

In the auto-snooze schema for a digital alarm clock with snooze facility, the alarm output as well as the snooze facility of the clock are used. When the alarm’s output goes high at the predetermined time, transistor BC547 conducts to trigger pin 2 of IC1. As a result, output pin 3 of IC1 goes high and it makes the alarm sound as well as triggers the snooze. This results in sounding of the alarm for=1.1×VR1×C1 seconds and turning the alarm output off so that pin 2 gets triggered only for a moment. After the snooze time (9 minutes for clock chip MM5387) programmed in the clock IC is over, the alarm output goes high and triggers IC1 again, and this process continues until the alarm-off switch of the clock is pressed.




On the other hand, in the auto-snooze schema for alarm clocks without snooze facility, first set presets VR2 and VR3, using the formula t=1.1RC, such that the time period of IC3 is less than the time period of IC2. For example, let the time constant of IC3 be 10 seconds and that of IC2 be 7 minutes. In such a setting the snooze time is 6 minutes 50 seconds and alarm-on time is 10 seconds.

In normal situation, the input of NAND gate N2 is low and thus its output at pin 4 is high. Consequently, the input at pin 2 of N1 is high. On the other hand, the input at pin 1 of N1 is kept low via resistor R3. At the predetermined time, when the alarm output from the clock goes high (also making pin 1 of N1 high), it makes output pin 3 of N1 low, which triggers both the monostables (IC2 and IC3) at pin 2. As a result, the input of gate N2 goes high and hence its output pin 4 as also pin 2 of gate N1 go low. Thus the output of N1 goes high immediately.

The output of IC3 switches on the alarm schema and it sounds for 10 seconds. The output of IC2 remains high for 7 minutes. Diode 1N4148 prevents the alarm from staying ‘on’ after 10 seconds. After 7 minutes, the inputs of N2 go low and thus monostable IC2 gets triggered once again. This process continues as long as the alarm output of the clock is high.

The entire schema can be powered from the 5V DC power supply of the clock. For louder sound you can use any alarm schema with a suitable power supply in place of the piezobuzzer.